❑What is finFET?
❑Structure and width calculation of finFET
❑How it works?
❑Planar v/s finFET w.r.t layout
❑Advantages and drawbacks
Before going further please go through knowledge on MOSFET structure, Working and Fabrication and Short Channel effects in MOSFET.
❑Innovative design of the MOSFET; typically built on SOI substrate on which silicon is etched into “fin”-like shaped body of the transistor; the gate is wrapped around and over the “fin” which also acts as a transistor’s channel.
❑Fin comes from the structure i.e. looks like fins of a FISH.
❑First developed by Chenming Hu and his colleagues.
What is FinFET
❑In the finFET the silicon body has been rotated on its edge into a vertical orientation so only source and drain regions are placed horizontally about the body, as in a conventional planar FET.
❑A gate can also be fabricated at the top of the fin, in which case it is a triple gate FET.
Width of a FinFET with n fins: W = 2*n*h == (2*h+Tfin)*n
Single gate, multiple source and drains i.e. fins.
❑The width of a finFET is quantized due to the vertical gate structure.
❑The fin height determines the minimum transistor width (Wmin). With the two gates of a single-fin FET tied together, Wmin is
Wmin = 2 × Hfin + Tfin
Where Hfin is the height of the fin and Tfin is the thickness of the fin.
❑Hfin is the dominant component of the transistor width because Hfin is fixed in a FinFET technology, multiple parallel fins are utilized to increase the width and current of a FinFET . ❑The total physical transistor width of a tied-gate FinFET with n parallel fins is: Wtotal = n × Wmin = n× (2 × Hfin + Tfin ).
Less Area – More Width
Functionality of finFETs
❑Functionality of finFETs is same as MOSFET.
➢Functionality of MOSFET ❖A cross section through an MOSFET, when the gate voltage VGS is below the threshold for making a conductive channel; there is little or no conduction between the terminals drain and source; the switch is off.
❖When the gate is more than threshold(Vth), it attracts charges, inducing a conductive channel in the substrate below the oxide, which allows charges to flow between the doped terminals; the switch is on.
Layout Wise Difference
finFETs in STD cells
●Short channel effects (SCE) includes DIBL (Drain Induced Barrier Lowering) and Ion and Ioff.
Advantages with finfet include
●Reduced Short Channel Effect(SCE)
●Operated at lower operating voltages
•SCE- An effect whereby a MOSFET in which the channel length is the same order of magnitude as the depletion-layer widths (xdD, xdS) of the source and drain junction, behaves differently from other MOSFETs. •SCE are – DIBL, Surface scattering, Velocity Saturation, Impact ionization, Hot electron effect etc.., •Issues in planar submicron tech – Vt reduction, sub threshold leakage,
SCE- An effect whereby a MOSFET in which the channel length is the same order of magnitude as the depletion-layer widths (xdD, xdS) of the source and drain junction, behaves differently from other MOSFETs.
❑Parameters which effects SCE.
➢Vth roll off
❖Threshold voltage of a MOSFET decrease with decrease in channel length called Vth Roll Off.
❖It is the accumulative effects of many leakages in the MOSFET which causes more power dissipation.
➢DIBL drain induced barrier lowering
❖In small geometry MOSFET’s, the potential barrier is controlled by both gate to source voltage Vgs and drain to source voltage Vds. If Vds is increased, the potential barrier in the channel decreases, leading to DIBL.
➢Hot carrier effects
❖a phenomenon in solid-state electronic devices where an electron or a “hole” gains sufficient kinetic energy to overcome a potential barrier necessary to break an interface state.
• In short channel devices source to drain distance is comparable to the depletion width in the vertical direction.
• The source and drain depletion regions now penetrate into the channel length resulting in part of channel already being depleted. Thus gate voltage has to invert less bulk charge to turn on transistor.
• Hot-carrier injection is one of the mechanisms that adversely affects the reliability of semiconductors of solid-state devices.
• The reduction in potential barrier between Drain and Source eventually allows the current flow between source and drain even if the Vgs is lower than the threshold voltage.
Reduction Technique of Short Channel Effects
●Process Level Technique
➢To Minimize the SCE a sufficiently large Aspect ratio (AR) of device is required.
● AR = lateral dimension/vertical dimension.
➢Where εsi and εox are silicon and oxide permittivity;
➢L channel length
➢tox gate oxide thickness
➢Wdm depletion depth
➢ Xj junction depth
●We can see that reducing tox, Wdm, Xj will reduce the SCE of a MOSFET.
●Circuit Level Technique
➢Multiple Vth Designs
❖Multi threshold-voltage CMOS
❖Variable Threshold Voltage Double-gate dynamic threshold SOI CMOS
How the SCE is reduced in finFETs
❑Ultra thin Si fin for suppression of short channel effects.
➢Most of leakage occurs in the region away from the channel in body.
➢No Overlapping of source and drain below gate.
➢Gate last process with low VT, high k gate dielectrics.
➢ The separate biasing in FinFET device easily provides multiple threshold voltages.
➢Due to better control over Vth, Tox can be increased which reduce the Gate Leakage.
❑Raised source/drain to reduce parasitic resistance and improve current drive
Manufacturing of FinFET’s
– SIDE-WALL IMAGE TRANSFER (SIT)
❑A Spacer is a film layer formed on the side wall of a pre-patterned feature.
❑As there are two spacers for every Mandrel, the fin density doubles
➢First pattern i.e. Mandrel
➢Deposition of mask material i.e. spacer
➢Etching to form side wall spacers
➢Removal of first pattern (Mandrel)
➢Etching using remaining spacers as mask
➢Removal of spacer, leaving final pattern i.e. fins.
finFET – Advantages
❑Reduced Short Channel Effect(SCE)
❑Operated at lower operating voltages
❑Fabrication of FinFET is compatible with CMOS process
❑10nm gate length, 12 nm fin width device has been fabricated and shows good performance
finFET – drawbacks
❑Width is quantized.
❑The β ratio is a quantized number i.e. fine tuning of β ratio is not possible ❑Complex Design rules. [ •Beta ratio is critical factor mainly in SRAM & Analog design and it is quantized. ]
❑An average of 25% increase in drive current with FINFET devices
➢More current through the same metal interconnects -> EM issue.
➢Fringe cap between gate and top/bottom S/D.
➢Complex fabrication steps